A host interface that connects to a bus, such as a Peripheral Component Interconnect (PCI) bus, may include a core. The core manages control circuitry responsible for data transfer to and from a device, such as a storage device, coupled to the bus. Data transfer and other commands may be placed in a queue managed by the core. The core advances from each queue entry to the next, checking a validity flag to determine if the command needs to be issued and a direction flag to determine if the command is a bus read or a bus write instruction. The core does not begin filling an outbound pipeline until actually reaching the command. Higher speed host interfaces such as PCI-X 533 and PCI Express require deep queues. These deep queues add latency to the interface, thereby degrading performance. Deep queues in the bus interface controller add substantial startup latency to outbound (i.e., bus write) commands to fill the pipeline. For example, if the seventh command queue entry were the first write command, then the core would advance through the first six entries by completing READ commands before beginning to fetch the data needed to complete the first WRITE command. Thus, there may be substantial delay between the completion of the sixth READ command and the core beginning the first WRITE command on that bus because the bus would go idle while the core collected the data it needed.
Two approaches have attempted to solve the problem of extended queue latencies. The first solution, shallower pipelines and/or tighter tie-in between core logic and bus interface, is impractical for high speed interfaces which do not allow the interface to be throttled (such as PCI-X and PCI Express). Tying core logic more tightly to the host interface can reduce latency but at the expense of reusability on future interfaces and at the expense of distributing complexity across multiple agents versus a single interface core. The second solution, next command lookahead, only checks the queue entry immediately following the current one and thus may not fully mask pipe fill latency if the current command is small.
Therefore, it would be desirable to provide a more efficient queue management method to reduce overall queue processing time.